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general description the MAX15023 dual, synchronous step-down controller operates from a 5.5v to 28v or 5v 10% input voltage range and generates two independent output voltages. each output is adjustable from 85% of the input voltage down to 0.6v and supports loads of 12a or higher. input voltage ripple and total rms input ripple current are reduced by interleaved 180 out-of-phase operation. the MAX15023 offers the ability to adjust the switching frequency from 200khz to 1mhz with an external resistor. the MAX15023s adaptive synchronous rectification elimi- nates the need for external freewheeling schottky diodes. the device also utilizes the external low-side mosfets on-resistance as a current-sense element, eliminating the need for a current-sense resistor. this protects the dc- dc components from damage during output overloaded conditions or output short-circuit faults without requiring a current-sense resistor. hiccup-mode current limit reduces power dissipation during short-circuit conditions. the MAX15023 includes two independent power-good out- puts and two independent enable inputs with precise turn-on/turn-off thresholds, which can be used for supply monitoring and for power sequencing. additional protection features include cycle-by-cycle, low-side, sink peak current limit, and thermal shutdown. cycle-by-cycle, low-side, sink peak current limit prevents reverse inductor current from reaching dangerous levels when the device is sinking current from the output. the MAX15023 also allows prebiased startup without dis- charging the output and features adaptive internal digital soft-start. this new proprietary feature enables monoton- ic charging of externally large output capacitors at start- up, and achieves good control of the peak inductor current during hiccup-mode short-circuit protection. the MAX15023 is available in a space-saving and ther- mally enhanced 4mm x 4mm, 24-pin tqfn-ep pack- age. the device operates over the -40c to +85c extended temperature range. applications point-of-load regulators set-top boxes lcd tv secondary supplies switches/routers power modules dsp power supplies features 5.5v to 28v or 5v ?0% input supply range 0.6v to (0.85 x v in ) adjustable outputs adjustable 200khz to 1mhz switching frequency guaranteed monotonic startup into a prebiased load lossless, cycle-by-cycle, low-side, source peak current limit with adjustable, temperature- compensated threshold cycle-by-cycle, low-side, sink peak current- limit protection proprietary adaptive internal digital soft-start ?% accurate voltage reference internal boost diodes adaptive synchronous rectification eliminates external freewheeling schottky diodes hiccup-mode short-circuit protection and thermal shutdown power-good outputs and analog enable inputs for power sequencing MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller ________________________________________________________________ maxim integrated products 1 23 24 22 21 *ep *exposed pad (connect to ground). 8 7 9 en1 pgood1 dl1 pgnd1 10 fb1 fb2 pgood2 dl2 comp2 pgnd2 12 lim2 456 17 18 16 14 13 lim1 comp1 dh2 dh1 bst1 lx1 MAX15023 en2 v cc 3 15 in 20 + 11 bst2 sgnd 19 12 lx2 rt tqfn top view pin configuration ordering information 19-4219; rev 1; 2/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package MAX15023etg+ -40c to +85c 24 tqfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad.
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = 12v, r t = 33k , c vcc = 4.7f, c in = 1f, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 3) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: these power limits are due to the thermal characteristics of the package, absolute maximum junction temperature (150c), and the jedec 51-7 defined setup. maximum power dissipation could be lower, limited by the thermal shutdown protection included in this ic. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial . in to sgnd.............................................................-0.3v to +30v bst_ to v cc ............................................................-0.3v to +30v lx_ to sgnd .............................................................-1v to +30v en_ to sgnd............................................................-0.3v to +6v pgood_ to sgnd .................................................-0.3v to +30v bst_ to lx_ ..............................................................-0.3v to +6v dh_ to lx_ ...........................................-0.3v to (v bst_ + 0.3v) dl_ to pgnd_ ............................................-0.3v to (v cc + 0.3v) sgnd to pgnd_ .................................................. -0.3v to +0.3v v cc to sgnd................-0.3v to the lower of +6v or (v in + 0.3v) all other pins to sgnd...............................-0.3v to (v cc + 0.3v) v cc short circuit to sgnd.........................................continuous v cc input current (in = v cc , internal ldo not used) ......600ma pgood_ sink current ........................................................20ma continuous power dissipation (t a = +70c)(note 1) 24-pin tqfn-ep (derate 27.8mw/c above +70c) ..2222.2mw junction-to-case thermal resistance ( jc ) 24-pin tqfn-ep ..............................................................3c/w junction-to-ambient thermal resistance ( ja )(note 2) 24-pin tqfn-ep ............................................................36c/w operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c storage temperature range .............................-60c to +150c lead temperature (soldering, 10s) .................................+300c parameter symbol conditions min typ max units general 5.5 28 input voltage range v in v in = v cc 4.5 5.5 v quiescent supply current i in v fb1 = v fb2 = 0.9v, no switching 4.5 6 ma standby supply current i in_sby v en1 = v en2 = sgnd 0.21 0.35 ma v cc regulator 6v < v in < 28v, i load = 5ma output voltage v cc v in = 6v, 1ma < i load < 100ma 5.00 5.2 5.50 v v cc regulator dropout i load = 100ma 0.07 v v cc short-circuit output current v in = 5v 150 250 ma v cc undervoltage lockout v cc_uvlo v cc falling 3.6 3.8 4 v v cc undervoltage lockout hysteresis 430 mv error amplifier (fb_, comp_) fb_ input voltage set-point v fb_ 594 600 606 mv fb_ input bias current i fb_ v fb_ = 0.6v -250 +250 na fb_ to comp_ transconductance g m i comp = 40a 650 1200 1900 s amplifier open-loop gain no load 80 db amplifier unity-gain bandwidth 10 mhz
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units comp_ swing (high) 2.4 v comp_ swing (low) no load at comp_ 0.6 v comp_ source/sink current i comp_ | i comp_ |, v comp_ = 1.5v 45 80 120 a enable (en_) en_ input high v en_h en_ rising 1.15 1.20 1.25 v en_ input hysteresis v en_hys 150 mv en_ input leakage current i leak_en_ -250 +250 na oscillator switching frequency f sw each converter 460 500 540 khz switching frequency adjustment range (note 4) 200 1000 khz pwm ramp peak-to-peak amplitude v ramp 1.42 v pwm ramp valley v valley 0.72 v phase shift between channels from dh1 to dh2 rising edges 180 degrees minimum controllable on-time 60 100 ns maximum duty cycle 86 87.5 % output drivers low, sinking 100ma, v bst_ - v lx_ = 5v 1 dh_ on-resistance h i g h, sour ci ng 100m a, v b s t _ - v l x _ = 5v 1.2 low, sinking 100ma, v cc = 5.2v 0.75 dl_ on-resistance high, sourcing 100ma, v cc = 5.2v 1.4 sinking 3 dh_ peak current c load = 10nf sourcing 2 a sinking 3 dl_ peak current c load = 10nf sourcing 2 a dh_, dl_ break-before-make time (dead time) 15 ns soft-start soft-start duration 2048 switching cycles reference voltage steps 64 steps electrical characteristics (continued) (v in = 12v, r t = 33k , c vcc = 4.7f, c in = 1f, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 3)
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in = 12v, r t = 33k , c vcc = 4.7f, c in = 1f, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 3) parameter symbol conditions min typ max units current limit/hiccup cycle-by-cycle, low-side, source peak current-limit threshold adjustment range source peak limit = v lim_ /10 30 300 mv lim_ reference current i lim_ v lim_ = 0.3v to 3v, t a = +25c 45 50 55 a lim_ reference current tc v lim_ = 0.3v 2400 ppm/c number of consecutive current- limit events to hiccup 7 events hiccup timeout out of soft-start 7936 switching cycles cycle-by-cycle, low-side, sink peak current-limit sense voltage v l im _ / 20 v boost boost switch resistance v in = v cc = 5.2v, i bst_ = 10ma 4.5 8 power-good outputs v fb_ rising 88.5 92.5 96.5 pgood_ threshold v fb_ falling 85.5 89.5 93.5 % v fb ( n om in a l ) pgood_ output leakage i leak_pgd v pgood_ = 28v, v en_ = 5v, v fb_ = 0.8v 1 a pgood_ output low voltage v pgood_l i pgood_ = 2ma, en_ = sgnd 0.4 v thermal shutdown thermal shutdown threshold +150 c thermal shutdown hysteresis temperature falling 20 c note 3: all electrical characteristics limits over temperature are 100% tested at room temperature and guaranteed by design over the specified temperature range. note 4: select r t as rk fkhz has a t sw () (()) ( . = 24806 24806 1 0663 1 1 farad unit).
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller _______________________________________________________________________________________ 5 efficiency vs. load current MAX15023 toc01 load current (a) efficiency (%) 10 1 35 40 45 50 55 60 65 70 75 80 85 90 95 30 0.1 100 v in = 12v v out1 = 1.2v v out1 = 3.3v efficiency vs. load current MAX15023 toc02 load current (a) efficiency (%) 10 1 35 40 45 50 55 60 65 70 75 80 85 90 95 100 30 0.1 100 v out1 = 1.2v v out1 = 3.3v v in = v cc = 5v output voltage change vs. load current MAX15023 toc03 load current (a) output voltage change (%) 10 8 6 4 2 99.2 99.4 99.6 99.8 100.0 100.2 100.4 100.6 100.8 101.0 99.0 012 out1 v cc voltage vs. load current MAX15023 toc04 load current (ma) supply voltage (v) 135 120 15 30 45 75 90 60 105 5.05 5.10 5.15 5.20 5.25 5.30 5.35 5.40 5.00 0 150 v cc voltage vs. in voltage MAX15023 toc05 in voltage (v) v cc voltage (v) 24 20 16 12 8 4.15 4.30 4.45 4.60 4.75 4.90 5.05 5.20 5.35 5.50 4.00 428 i load = 5ma i load = 50ma v cc voltage vs. temperature MAX15023 toc06 temperature ( c) supply voltage (v) 30 35 10 -15 5.05 5.10 5.15 5.20 5.25 5.30 5.35 5.40 5.45 5.50 5.00 -40 85 i load = 5ma switching frequency vs. r t MAX15023 toc07 r t (k ) switching frequency (khz) 80 70 50 60 30 40 20 200 300 400 500 600 700 800 900 1000 1100 1200 1300 100 10 90 switching frequency vs. temperature MAX15023 toc08 temperature ( c) switching frequency (khz) 60 35 10 -15 250 300 350 400 450 500 550 600 650 700 750 800 200 -40 85 r t = 22.1k r t = 33.2k r t = 66.5k i in current vs. switching frequency MAX15023 toc09 switching frequency (khz) i in current (ma) 900 800 700 600 500 400 300 30 60 90 120 150 180 210 0 200 1000 v in = 12v c dl = c dh = 10nf c dl = c dh = 4.7nf c dl = c dh = 1nf c dl = c dh = 0nf typical operating characteristics (supply = in = 12v, unless otherwise noted. see typical application circuit of figure 6.)
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller 6 _______________________________________________________________________________________ typical operating characteristics (continued) (supply = in = 12v, unless otherwise noted. see typical application circuit of figure 6.) i in + i vcc current vs. switching frequency MAX15023 toc10 switching frequency (khz) i in + i vcc current (ma) 900 800 700 600 500 400 300 30 60 90 120 150 180 210 0 200 1000 v in = v cc = 5v c dl_ = c dh_ = 10nf c dl_ = c dh_ = 4.7nf c dl_ = c dh_ = 1nf c dl = c dh = 0nf en_ turn-on and turn-off threshold vs. temperature MAX15023 toc11 temperature ( c) en_ turn-on and turn-off thresholds 60 35 10 -15 1.025 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.000 -40 85 en_ rising en_ falling lim_ current vs. temperature MAX15023 toc12 temperature ( c) lim_ current ( a) 60 35 10 -15 40 42 44 46 48 50 52 54 56 58 60 38 -40 85 i lim2 i lim1 shutdown current vs. temperature MAX15023 toc13 temperature ( c) shutdown current ( a) 60 35 10 -15 205 210 215 220 225 230 200 -40 85 current-limit threshold vs. r lim MAX15023 toc14 r lim (k ) current-limit threshold (mv) 55 50 40 45 15 20 25 30 35 10 30 60 90 120 150 180 210 240 270 300 0 560 source current limit sink current limit load transient on out1 MAX15023 toc15 10 s/div v out1 (ac-coupled) 100mv/div v out2 (ac-coupled) 50mv/div i out1 5a/div load transient on out2 MAX15023 toc16 10 s/div v out2 (ac-coupled) 200mv/div v out1 (ac-coupled) 100mv/div i out2 2a/div
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller _______________________________________________________________________________________ 7 typical operating characteristics (continued) (supply = in = 12v, unless otherwise noted. see typical application circuit of figure 6.) startup and disable from en MAX15023 toc19 2ms/div v en2 5v/div v in 10v/div v out2 2v/div v pgood2 5v/div i out2 = 500ma startup and turn-off from in MAX15023 toc20 4ms/div v in 10v/div v out1 1v/div v pgood1 5v/div en1 = en2 = v cc i out1 = 1.2a startup and turn-off from in MAX15023 toc21 4ms/div v in 10v/div v out2 2v/div v pgood2 5v/div i out2 = 500ma startup into prebiased output (0.5v prebiased) MAX15023 toc22 2ms/div v out1 500mv/div 0v line-transient response MAX15023 toc17 2ms/div v in 5v/div v out1 (ac-coupled) 50mv/div v out2 (ac-coupled) 100mv/div startup and disable from en MAX15023 toc18 2ms/div v en1 5v/div v in 10v/div v out1 500mv/div v pgood1 5v/div i out1 = 1.2a
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller 8 _______________________________________________________________________________________ typical operating characteristics (continued) (supply = in = 12v, unless otherwise noted. see typical application circuit of figure 6.) startup into prebiased output (1v prebiased) MAX15023 toc23 2ms/div v out1 500mv/div 0v startup into prebiased output (1.5v prebiased) MAX15023 toc24 2ms/div v out1 500mv/div 0v dh_ and dl_ disoverlap MAX15023 toc25 20ns/div v dh1 10v/div v dl1 5v/div v lx1 10v/div i out1 = 5a dh_ and dl_ disoverlap MAX15023 toc26 20ns/div v dh1 10v/div v dl1 5v/div v lx1 10v/div i out1 = 5a out-of-phase switching forms MAX15023 toc27 1 s/div v lx1 10v/div v lx2 10v/div i lx1 5a/div i lx2 2a/div i out1 = 5a i out2 = 2.5a sink current-limit waveforms MAX15023 toc28 100 s/div v out1 200mv/div v lx1 20v/div i lx1 2a/div 1.5v prebiased
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller _______________________________________________________________________________________ 9 pin description pin name function 1 fb1 feedback input for regulator 1. connect fb1 to a resistive divider between output 1 and sgnd to adjust the output voltage between 0.6v and (0.85 x input voltage (v)). see the setting the output voltage section. 2 en1 active-high enable input for regulator 1. when the voltage at en1 exceeds 1.2v (typ), the controller begins regulating out1. when the voltage falls below 1.05v (typ), the regulator is turned off. the en1 input can be used for power sequencing and as a secondary uvlo. connect en1 to v cc for always-on applications. 3 en2 active-high enable input for regulator 2. when the voltage at en2 exceeds 1.2v (typ), the controller begins regulating out2. when the voltage falls below 1.05v (typ), the regulator is turned off. the en2 input can be used for power sequencing and as a secondary uvlo. connect en2 to v cc for always-on applications. 4 pgood1 power-good output (open drain) for channel 1. to obtain a logic signal, pull up pgood1 with an external resistor connected to a positive voltage below 28v. 5 dl1 low-side gate-driver output for regulator 1. dl1 swings from v cc to pgnd1. dl1 is low before v cc reaches the uvlo rising threshold voltage. 6 pgnd1 low-side gate-driver supply return (regulator 1). connect to the source of the low-side mosfet of regulator 1. 7 lx1 external inductor connection for regulator 1. connect lx1 to the switched side of the inductor. lx1 serves as the lower supply rail for the dh1 high-side gate driver and as sensing input of the synchronous mosfets v ds drop (drain terminal). 8 bst1 boost flying-capacitor connection for regulator 1. connect a ceramic capacitor with a minimum value of 100nf between bst1 and lx1. 9 dh1 high-side gate-driver output for regulator 1. dh1 swings from lx1 to bst1. dh1 is low before v cc reaches the uvlo rising threshold voltage. 10 dh2 high-side gate-driver output for regulator 2. dh2 swings from lx2 to bst2. dh2 is low before v cc reaches the uvlo rising threshold voltage. 11 bst2 boost flying-capacitor connection for regulator 2. connect a ceramic capacitor with a minimum value of 100nf between bst2 and lx2. 12 lx2 external inductor connection for regulator 2. connect lx2 to the switched side of the inductor. lx2 serves as the lower supply rail for the dh2 high-side gate driver and as sensing input of the synchronous mosfets v ds drop (drain terminal).
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller 10 ______________________________________________________________________________________ pin description (continued) pin name function 13 pgnd2 low-side gate-driver supply return (regulator 2). connect to the source of the low-side mosfet of regulator 2. 14 dl2 low-side gate-driver output for regulator 2. dl2 swings from v cc to pgnd2. dl2 is low before v cc reaches the uvlo rising threshold voltage. 15 pgood2 power-good output (open drain) for channel 2. to obtain a logic signal, pull up pgood2 with an external resistor connected to a positive voltage below 28v. 16 v cc internal 5.2v linear regulator output and the devices core supply. when using the internal regulator, bypass v cc to sgnd with a 4.7f minimum low-esr ceramic capacitor. if v cc is connected to in for 5v operation, then a 2.2f ceramic capacitor is adequate for decoupling (see the typical application circuits ). 17 fb2 feedback input for regulator 2. connect fb2 to a resistive divider between output 2 and sgnd to adjust the output voltage between 0.6v and (0.85 x input voltage (v)). see the setting the output voltage section. 18 comp2 compensation pin for regulator 2. see the compensation section. 19 rt oscillator-timing resistor input. connect a resistor from rt to sgnd to set the oscillator frequency from 200khz to 1mhz (see the setting the switching frequency section). 20 sgnd signal ground. connect sgnd to the sgnd plane. sgnd also serves as sensing input of the synchronous mosfets v ds drop (source terminals) for both channels. 21 in internal v cc regulator input. bypass in to sgnd with a 1f minimum ceramic capacitor when the internal linear regulator (v cc ) is used. when operating in the 5v 10% range, connect in to v cc . 22 lim2 current-limit adjustment for regulator 2. connect a resistor (r lim2 ) from lim2 to sgnd to adjust the current-limit threshold (v ith2 ) from 30mv (r lim2 = 6k ) to 300mv (r lim2 = 60k ). see the setting the cycle-by-cycle low-side source peak current limit section. 23 lim1 current-limit adjustment for regulator 1. connect a resistor (r lim1 ) from lim1 to sgnd to adjust the current-limit threshold (v ith1 ) from 30mv (r lim1 = 6k ) to 300mv (r lim1 = 60k ). see the setting the cycle-by-cycle low-side source peak current limit section. 24 comp1 compensation pin for regulator 1. see the compensation section. ep exposed paddle. connect ep to a large copper plane at sgnd potential to improve thermal dissipation. do not use as the main ics sgnd ground connection.
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller ______________________________________________________________________________________ 11 functional diagram oscillator enable logic vref rt en1 enable1 comparator thermal shutdown bandgap reference startup bias vref vref = 0.6v vref en2 sgnd in lim2 lim1 v cc enable2 comparator in uvlo v cc uvlo internal voltage regulator lim current generator MAX15023 gen vref ck2 ck1 enable1 enable2 vref ck2 lim2 sgnd lim1 ck1 enable1 enable1 g m v ref enable2 dc-dc converter 2 dc-dc converter 1 soft-start/ stop logic and hiccup logic comp2 bst2 dh2 pgnd2 pgood2 fb2 dl2 lx2 MAX15023 vref 0.925 x v ref ck1 fb1 dac_vref pwm comparator ramp generator boost driver low-side driver sink current-limit comparator pgood comparator source current-limit comparator high- side driver pwm pwm control logic ramp gatep hiccup timeout hiccup hiccup v cc lim1/20 lim1/10 hiccup timeout comp1 bst1 dh1 lx1 dl1 pgnd1 fb1 pgood1
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller 12 ______________________________________________________________________________________ detailed description the MAX15023 dual, synchronous, step-down con- troller operates from a 5.5v to 28v or 5v 10% input voltage range and generates two independent output voltages. as long as the controllers input bias voltage is within the specified range, the input power bus can also be lower than 4.5v and step-down conversion from a 3.3v rail is also possible. both output voltages can be set from 0.6v to 85% of regulators input volt- age. each output can support loads of 12a or higher. the switching sequence of the regulators is interleaved with 180 out-of-phase operation, so that input voltage ripple and total rms input ripple current are reduced. enable inputs with precise turn-on/off threshold (4.2%) allow accurate external uvlo settings. power- good (pgood) open-drain outputs can be used for supply sequencing. the MAX15023s capability to provide low output volt- ages (down to 0.6v) and high output current (in excess of 12a) makes it ideal for applications where a 5v or 12v bus is postregulated to deliver low voltages and high currents, such as in set-top boxes. the switching frequency is adjustable from 200khz to 1mhz using an external resistor. the MAX15023s adaptive synchronous rectification eliminates the need for external freewheeling schottky diodes. the MAX15023 utilizes voltage-mode control and exter- nal compensation. the device also utilizes cycle-by- cycle low-side source peak current limit for overcurrent protection, where the external low-side mosfets on- resistance is used as a current-sense element during the inductor freewheeling time, eliminating the need for a current-sense resistor. the current-limit threshold voltage is resistor adjustable independently on each regulator from 30mv to 300mv and is temperature compensated, so that the effects of the mosfets r ds(on) variation over temperature are reduced. hiccup-mode current limit reduces average current and power dissipation during a prolonged short-circuit condition. the MAX15023 also features a proprietary adaptive internal digital soft-start and allows prebias startup without discharging the output. adaptive digital soft- start, by acting on the loop voltage reference, automati- cally prolongs the soft-start time, if the current-limit threshold is reached during the soft-start sequence. this increases the ability to smoothly bring up a large, unknown amount of output capacitance. also, since soft-start is invoked during hiccup-mode short-circuit protection, the same voltage reference rollback algo- rithm achieves good control of the peak inductor cur- rent during steady short-circuit or overload conditions. an additional protection feature (cycle-by-cycle low- side sink peak current limit) prevents the regulators from sinking excessive amount of current if the prebias volt- age exceeds the programmed steady-state regulation level, or if another voltage source is trying to force the output above that. this way, the synchronous rectifier mosfet and the body diode of the high-side mosfet do not experience dangerous levels of current stress while the regulator is sinking current from the output. thermal shutdown protects the MAX15023 from exces- sive power dissipation. dc-dc pwm controller the MAX15023 step-down controller uses a pwm volt- age-mode control scheme (see the functional diagram ) for each channel. control loop compensation is external for providing maximum flexibility in choosing the operating frequency and output lc filter compo- nents. an internal transconductance error amplifier pro- duces an integrated error voltage at comp_ that helps provide higher dc accuracy. the voltage at comp_ sets the duty cycle using a pwm comparator and a ramp generator. on the rising edge of its internal clock, the high-side n-channel mosfet of each regulator turns on and remains on until either the appropriate duty cycle or the maximum duty cycle is reached. during the high-side mosfets on-time, the inductor current ramps up. during the second-half of the switch- ing cycle, the high-side mosfet turns off and the low- side n-channel mosfet turns on. now the inductor releases the stored energy as its current ramps down, providing current to the output. under overload condi- tions, when the inductor current exceeds the selected cycle-by-cycle low-side source peak current-limit threshold (see the current-limit circuit (lim_) section), the high-side mosfet does not turn on at the subse- quent clock rising edge and the low-side mosfet remains on to let the inductor current ramp down. interleaved out-of-phase operation the two independent regulators in the MAX15023 oper- ate 180 out-of-phase to reduce input filtering require- ments, reduce electromagnetic interference (emi), and improve efficiency. this effectively lowers component cost and saves board space, making the MAX15023 ideal for cost-sensitive applications.
MAX15023 the internal oscillator frequency is divided down to obtain separated clock signals for each regulator. the phase difference of the two clock signals is 180, so that the high-side mosfets turn on out-of-phase. the instan- taneous input current peaks of both regulators no longer overlap, resulting in reduced rms ripple current and input voltage ripple. as a result, this allows an input capacitor with a lower ripple-current rating to be used or allows the use of fewer or less expensive capacitors, as well as reduces emi filtering and shielding requirements. internal 5.2v linear regulator the MAX15023s internal functions and mosfet drivers are designed to operate from a 5v 10% supply volt- age. if the available supply voltage exceeds 5.5v, a 5.2v internal low-dropout linear regulator is used to power internal functions and the mosfet drivers at v cc . if an external 5v 10% supply voltage is available, then in and v cc can be tied to the 5v supply. the maxi- mum regulator input voltage (v in ) is 28v. the regulators input (in) must be bypassed to sgnd with a 1f ceramic capacitor when the regulator is used. bypass the regulators output (v cc ) with a 4.7f ceramic capacitor to sgnd. the v cc dropout voltage is typically 70mv, so when v in is greater than 5.5v, v cc is typically 5.2v. the MAX15023 also employs a uvlo circuit that disables both regulators when v cc falls below 3.8v (typ). the 430mv uvlo hysteresis prevents chattering on power-up/power-down. the internal v cc linear regulator can source up to 100ma to supply the ic, power the low-side gate dri- vers, recharge the external boost capacitors, and sup- ply small external loads. the current available for external loads depends on the current consumed for the mosfet gate drive. for example, when switched at 600khz, a single mosfet with 18nc total gate charge (at v gs = 5v) requires 18nc x 600khz ? 11ma. since four mosfets are driven and 6ma (max) is used by the internal con- trol functions, the current available for external loads is: (100 C (4 x 11) C 6)ma ? 50ma mosfet gate drivers (dh_, dl_) the dh_ and dl_ drivers are optimized for driving large size n-channel power mosfets. under normal operating conditions and after startup, the dl_ low-side drive waveform is always the complement of the dh_ high-side drive waveform (with controlled dead time to prevent cross-conduction or shoot-through). on each channel, an adaptive dead-time circuit monitors the dh and dl outputs and prevents the opposite-side mosfet from turning on until the other mosfet is fully off. thus, the circuit allows the high-side driver to turn on only when the dl_ gate driver has been turned off. similarly, it prevents the low-side (dl_) from turning on until the dh_ gate driver has been turned off. the adaptive driver dead time allows operation without shoot-through with a wide range of mosfets, minimizing delays, and maintaining efficiency. there must be a low- resistance, low-inductance path from the dl_ and dh_ drivers to the mosfet gates for the adaptive dead-time circuits to work properly. otherwise, because of the stray impedance in the gate discharge path, the sense circuit- ry could interpret the mosfet gates as off while the v gs of the mosfet is still high. to minimize stray imped- ance, use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). synchronous rectification reduces conduction losses in the rectifier by replacing the normal low-side schottky catch diode with a low-resistance mosfet switch. the internal pulldown transistor that drives dl_ low is robust, with a 0.75 (typ) on-resistance. this low on- resistance helps prevent dl_ from being pulled up dur- ing the fast rise time of the lx_ node, due to capacitive coupling from the drain to the gate of the low-side syn- chronous rectifier mosfet. high-side gate-drive supply (bst_) and internal boost switches the high-side mosfet is turned on by closing an inter- nal switch between bst_ and dh_. this provides the necessary gate-to-source voltage to turn on the high-side mosfet, an action that boosts the gate drive signal above v in . the boost capacitor connected between bst_ and lx_ holds up the voltage across the floating gate driver during the high-side mosfet on-time. the charge lost by the boost capacitor for delivering the gate charge is refreshed when the high-side mosfet is turned off and lx_ node swings down to ground. when the corresponding lx_ node is low, an internal high-volt- age switch connected between v cc and bst_ recharges the boost capacitor to the v cc voltage. the need for external boost diodes is negated. see the boost flying- capacitor selection section in the design procedure section to choose the right size of the boost capacitor. enable inputs (en_), adaptive soft-start and soft-stop the MAX15023 can be used to regulate two indepen- dent outputs. each of the two outputs can be turned on and off independently of one another by controlling the enable input of each phase (en1 and en2). a logic-high on each enable pin turns on the corre- sponding channel. then, the soft-start sequence is initi- ated by step-wise increasing the reference voltage of wide 4.5v to 28v input, dual-output synchronous buck controller ______________________________________________________________________________________ 13
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller 14 ______________________________________________________________________________________ the error amplifier. the duration of the soft-start ramp is 2048 switching cycles and the resolution is 1/64 of the steady-state regulation voltage. this allows a smooth increase of the output voltage. a logic-low on each en_ initiates a soft-stop sequence by stepping down the ref- erence voltage of the error amplifier. after the soft-stop sequence is completed, the mosfet drivers are both turned off. see figure 1 for more detail. connect en1 and en2 to v cc for always-on operation. owing to their accurate turn-on and turnCoff thresholds, en1 and en2 can be used as a uvlo adjustment input and for power sequencing together with the pgood_ outputs. (see the setting the enable input (en_) section). the adaptive action in the soft-start becomes visible if the cycle-by-cycle, low-side, source peak current limit is reached during the soft-start ramping sequence. in this case, the rate-of-rise of the internal reference is decreased, so that the pwm controller tries to regulate to the inductor current around its limit value, rather than the output voltage. the soft-start time can be prolonged up to 4096 clock cycles (twice the normal soft-start duration). this implementation allows the soft-start time to be automatically adapted to the time necessary to keep the lx current below the limit while charging the output capacitor. since soft-start is invoked by the hiccup-mode short- circuit protection, also see the hiccup mode overcurrent protection section for additional details. power-good outputs (pgood_) the MAX15023 includes two power-good comparators to monitor the regulators output voltages and detect the power-good threshold, fixed at 92.5% of the nomi- nal fb voltage. the pgood_ outputs are open-drain and should be pulled up with an external resistor to the supply voltage of the logic input they drive. this voltage should not exceed 28v. they can sink up to 2ma of current while low. v cc b cd e 2048 clk cycles 2048 clk cycles f g hi a uvlo en_ v out_ dac_vref_ dh_ dl_ uvlo undervoltage threshold value is provided in the electrical characteristics table. internal 5.2v linear regulator output. active-high enable input. regulator output voltage. regulator internal soft-start and soft-stop signal. regulator high-side gate-driver output. regulator low-side gate-driver output. v cc rising while below the uvlo threshold. en_ is low. v cc en_ v out_ dac_vref_ dh_ dl_ a symbol definition b v cc is higher than the uvlo threshold. en_ is low. en is pulled high. dh_ and dl_ start switching. normal operation. v cc drops below uvlo. v cc goes above uvlo threshold. dh_ and dl_ start switching. normal operation. en_ is pulled low. v out_ enters soft-stop. en_ is pulled high. dh_ and dl_ start switching. normal operation. v cc drops below uvlo. c d e f g h i symbol definition figure 1. MAX15023 detailed power-on/-off sequencing
MAX15023 each pgood_ goes high (high impedance) when the corresponding regulator output increases above 92.5% of its nominal regulated voltage. each pgood_ goes low when the corresponding regulator output voltage drops typically below 89.5% of its nominal regulated voltage. pgood_ can be used as power-on-reset or power sequencing for the two regulators. pgood_ asserts low during the hiccup timeout period. startup into a prebiased output when the controller starts into a prebiased output, the dh_/dl_ complementary switching sequence is inhibit- ed until the pwm comparator commands its first pwm pulse. until then, dh_ and dl_ are kept off so that the converter does not sink current from the output. the first pwm pulse occurs when the ramping reference voltage increases above the fb_ voltage or the internal soft-start time is over. current-limit circuit (lim_) the current-limit circuit employs a cycle-by-cycle low- side source peak and sink current-sensing algorithm that uses the on-resistance of the low-side mosfet as a current-sensing element, so that costly sense resis- tors are not required. the current-limit circuit is also temperature compensated to track the mosfets on- resistance variation over temperature. the current limit is adjustable on each channel with an external resistor at lim_ (see the typical application circuits ), and accommodates mosfets with a wide range of on- resistance characteristics (see the design procedure section). the adjustment range is from 30mv to 300mv for the cycle-by-cycle, low-side, source peak current limit, corresponding to resistor values of 6k to 60k . the cycle-by-cycle, low-side, source peak current-limit threshold across the low-side mosfet is precisely 1/10 the voltage seen at lim_, while the cycle-by-cycle, low- side, sink peak current-limit threshold is 1/20 the volt- age seen at lim_. the MAX15023 uses sgnd to sense the voltage of the source terminals of the low-side mosfets for both channels, and lx_ to sense the drain voltage of each low-side mosfet. carefully observe the pcb layout guidelines section to ensure that noise and systematic errors do not corrupt the current-sense signals seen by lx_ and sgnd on each channel. cycle-by-cycle, low-side, source peak current limit acts when the inductor current flows in the normal direction, and the drain (lx_) is more negative than source (sensed by sgnd) during the low-side mosfet on- time. if the magnitude of current-sense signal exceeds the cycle-by-cycle, low-side, source peak current-limit threshold during the low-side mosfet on-time, the controller does not initiate a new pwm cycle and lets the inductor current decay in the next cycle. since cycle-by-cycle, low-side, source peak current sensing is employed, the actual peak current is greater than the current-limit threshold by an amount equal to the induc- tor ripple current. therefore, the exact current-limit characteristic and maximum load capability are func- tions of the low-side mosfets on-resistance, current- limit threshold, inductor value, and input voltage. cycle-by-cycle, low-side, sink peak current limit is also implemented by monitoring the voltage drop across the low-side mosfet, but with opposite polarity (drain more positive than source). if this drop exceeds 1/20 the voltage at the corresponding lim_ pin at any time during the low-side mosfet on-time, the low-side mosfet is turned off and the inductor current flows from the output through the high-side mosfet back. if the cycle-by-cycle, low-side, sink peak current limit is activated, the dh_ and dl_ switching sequence is no longer complementary. hiccup mode overcurrent protection hiccup mode overcurrent protection reduces power dissipation during prolonged short-circuit or deep over- load conditions. after the soft-start sequence has been completed, on each switching cycle where the cycle-by-cycle, low-side, source peak current-limit threshold is reached, a 3-bit counter is incremented. the counter is decremented on each switching cycle where the threshold is not reached, and stopped at zero (000). if the cycle-by-cycle, low-side, source peak current- limit condition persists, the counter fills up reaching 111 (= 7 events). then, the controller stops both dl_ and dh_ drivers and waits for 7936 switching cycles (hic- cup timeout delay). after this delay, the controller initi- ates a new soft-start sequence. if cycle-by-cycle, low-side, source peak current-limit events occur during the soft-start time, turn-on cycles are still skipped to control the inductor current, but the fill-up of the 3-bit counter does not terminate the soft-start sequence. rather, the soft-start ramp is slowed down or rolled back based on the cycle-by-cycle, low-side, source peak current-limit events occurrences, so that the pwm controller tries to regulate the inductor current around its limit value, rather than the output voltage. this proprietary technique prevents the duty cycle from saturating, and limits the on-time and thus, the peak inductor current is reached every time the high-side mosfet is turned on. wide 4.5v to 28v input, dual-output synchronous buck controller ______________________________________________________________________________________ 15
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller 16 ______________________________________________________________________________________ in case of a nonideal short circuit applied at the output, the output voltage equals the output impedance times the limited inductor current during this phase. after reaching the maximum allowable limit of the soft-start duration (twice the normal soft-start time), the controller remains off for 7936 clock cycles before trying to soft-start again. undervoltage lockout the MAX15023 has an internal undervoltage lockout (uvlo) circuit to monitor the voltage on v cc . the uvlo circuit prevents the MAX15023 from operating if the voltages for the mosfet drivers or for the internal control functions are too low. the v cc falling threshold is 3.8v (typ), with 430mv hysteresis to prevent chatter- ing on the rising/falling edge of the supply voltage. before v cc reaches uvlo rising threshold voltage, dl_ and dh_ stay low to inhibit switching. thermal-overload protection thermal-overload protection limits total power dissipation in the MAX15023. when the devices die-junction tem- perature exceeds t j = +150c, an on-chip thermal sen- sor shuts down the device, forcing dl_ and dh_ low, allowing the ic to cool. the thermal sensor turns the device on again after the junction temperature cools by 20c. during thermal shutdown, the regulators shut down, and soft-start is reset. thermal-overload protection can be triggered by power dissipation in the ldo regula- tor, by excessive driving losses, or by both. therefore, carefully evaluate the total power dissipation (see the power dissipation section) to avoid unwanted triggering of the thermal-overload protection in normal operation. design procedure effective input voltage range although the MAX15023 controllers can operate from input supplies up to 28v and regulate down to 0.6v, the minimum voltage conversion ratio (v out /v in ) might be limited by the minimum controllable on-time. for proper fixed-frequency pwm operation, the voltage conversion ratio should obey the following condition: where t on(min) is 100ns (max) and f sw is the switching frequency in hertz. if the desired voltage conversion does not meet the above condition, then pulse skipping occurs to decrease the effective duty cycle. to avoid this, decrease the switching frequency or lower the input voltage v in . the maximum voltage conversion ratio is limited by the maximum duty cycle (d max ): where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pcb resistances. v drop2 is the sum of the resistances in the charging path, including high-side switch, inductor, and pcb resistances. in practice, the above condition should be met with ade- quate margin for good load-transient response. setting the enable input (en_) each controller has an enable input referenced to an analog voltage (1.2v). when the voltage exceeds 1.2v, the regulator is enabled. to set a specific turn-on threshold that can act as a secondary uvlo, a resistive divider circuit can be used (see figure 2) select r 2 (en_ to sgnd resistor) to a value lower than 200k . calculate r 1 (v mon to en_ resistor) with the fol- lowing equation: where v en_h_ = 1.2v (typical). rr v v mon en h 12 1 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? __ v v d d v (1 d ) v v out in max max drop2 max drop1 in < + ? ? v v tf out n on(min) sw i > en_ r 1 v mon r 2 ma15023 figure 2. adjustable enable voltage
MAX15023 setting the output voltage set the MAX15023 output voltage on each channel by connecting a resistive divider from the output to fb_ to sgnd (figure 3). select r 2 (fb_ to sgnd resistor) less than or equal to 16k . calculate r 1 (out_ to fb_ resis- tor) with the following equation: where v fb_ = 0.6v (typ) (see the electrical characteristics table) and v out_ can range from 0.6v to (0.85 x v in ). resistor r 1 also plays a role in the design of the type iii compensation network. if a type iii compensation network is used, make sure to review the values of r 1 and r 2 according to the type iii compensation network (see figure 5) section. setting the switching frequency the switching frequency, f sw , for each channel is set by a resistor (r t ) connected from rt to sgnd. the relationship between f sw and r t is: where f sw is in khz, r t is in k , and 24806 is in 1/farad. for example, a 600khz switching frequency is set with r t = 27.05k . higher frequencies allow designs with lower inductor values and less output capacitance. consequently, peak currents and i 2 r losses are lower at higher switching frequencies, but core losses, gate-charge currents, and switching loss- es increase. inductor selection three key inductor parameters must be specified for operation with the MAX15023: inductance value (l), inductor saturation current (i sat ), and dc resistance (r dc ). to select inductance value, the ratio of inductor peak-to-peak ac current to dc average current (lir) must be selected first. a good compromise between size and loss is a 30% peak-to-peak ripple current to average-current ratio (lir = 0.3). the switching fre- quency, input voltage, output voltage, and selected lir then determine the inductor value as follows: where v in , v out , and i out are typical values (so that efficiency is optimum for typical conditions). the switching frequency is set by r t (see the setting the switching frequency section). the exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, efficiency, and transient response requirements. lower inductor values minimize size and cost, but also improve transient response and reduce efficiency due to higher peak currents. on the other hand, higher inductance increases efficiency by reducing the rms current, but requires more output capacitance to meet load-transient specifications. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. the inductors saturation rating (i sat ) must be high enough to ensure that saturation can occur only above the max- imum current-limit value, given the tolerance of the low- side mosfets on-resistance and of the lim_ reference current (i lim ). on the other hand, these tolerances should not prevent the converter from delivering the rated load current (i load(max) ). combining these con- ditions, the inductor saturation current (i sat ) should be such that: where r ds(on,max) and r ds(on,typ) are the maximum and typical on-resistance of the low-side mosfet. for a given inductor type and value, choose the lir corre- sponding to the worst-case inductor tolerance. for lir = 0.4, and a +25% on the low-side mosfets r ds(on,max) , the inductor saturation current should be about 50% greater than the converters maximum load current. a variety of inductors from different manufac- turers can be chosen to meet this requirement (for example, coilcraft mss1278 series). i1i sat r ds(on,max) r ds(on,typ) load(max) >+ ? ? ? ? ? ? lir 2 l vvv v f i lir out in out in sw out = ? () r f t sw = 24806 1 0663 () . rr v v out fb 12 1 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? _ _ fb_ r 1 out_ r 2 ma15023 figure 3. adjustable output voltage wide 4.5v to 28v input, dual-output synchronous buck controller ______________________________________________________________________________________ 17
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller 18 ______________________________________________________________________________________ setting the cycle-by-cycle, low-side, source peak current limit the minimum current-limit threshold must be high enough to support the maximum expected load current with the worst-case low-side mosfet on-resistance value since the low-side mosfets on-resistance is used as the current-sense element. the inductors cycle-by-cycle, low-side, source peak current occurs at i load(max) minus half the ripple current. the ripple cur- rent is maximum when the inductor value is at the lower limit of its specified tolerance. the minimum value of the current-limit threshold voltage (v ith ) should be greater than the voltage on the low-side mosfet dur- ing the ripple-current valley: where r ds(on) is the on-resistance of the low-side mosfet in ohms. use the maximum value for r ds(on) from the low-side mosfets data sheet. to adjust the current-limit threshold, connect a resistor (r lim_ ) from lim_ to sgnd. the relationship between the current-limit threshold (v ith_ ) and r lim_ is: where r lim_ is in k and v ith_ is in mv. an r lim_ resistance range of 6k to 60k corresponds to a current-limit threshold of 30mv to 300mv. when adjusting the current limit, use 1% tolerance resistors to minimize errors in the current-limit threshold setting. input capacitor the input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuits switching. the two converters of the MAX15023 run 180 out-of- phase, thereby, effectively doubling the switching fre- quency at the input and lowering the input rms current. the input ripple waveform would be unsymmetrical due to the difference in load current and duty cycle between converter 1 and converter 2. in fact, the worst-case input rms current occurs when only one controller is operat- ing. the converter delivering the highest output power (v out x i out ) must be used in the formulas below: the input capacitor rms current requirement (i rms ) is defined by the following equation: i rms has a maximum value when the input voltage equals twice the output voltage (v in = 2v out ), so i rms(max) = i load(max) /2. choose an input capacitor that exhibits less than +10c temperature rise at the rms input current for optimal long-term reliability. the input voltage ripple is composed of v q (caused by the capacitor discharge) and v esr (caused by the esr of the capacitor). use low-esr ceramic capacitors with high ripple current capability at the input. assume the contribution from the esr and capacitor discharge are equal to 50%. calculate the input capacitance and esr required for a specified input voltage ripple using the following equations: where: and: where: all equations listed above are valid under the assump- tion that the input ports of both converters can be merged in the physical layout, so that only one input capacitor truly serves both converters. if this is not the case, additional low-esr, low-esl ceramic capacitors should be locally placed on each converters input port, connected between the drain of the high-side mosfet and the source of the low-side mosfet. output capacitor the key selection parameters for the output capacitor are capacitance value, esr, and voltage rating. these parameters affect the overall stability, output ripple volt- age, and transient response. the output ripple has two components: variations in the charge stored in the out- put capacitor, and the voltage drop across the capaci- tors esr caused by the current flowing into and out of the capacitor: ?? vvv ripple esr q ?+ d v v out in = c idd vf in out qsw = ? () 1 i vv v vf l l in out out in sw = ? () esr v i i in esr out l = + 2 ii vvv v rms load max out in out in = ? () () r v a lim ith _ _ = 10 50 vr i lir ith ds on max load max > ? ? ? ? ? ? ? (, ) ( ) 1 2
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller ______________________________________________________________________________________ 19 the output voltage ripple as a consequence of the esr and the output capacitance is: where i l is the peak-to-peak inductor current ripple (see the inductor selection section). these equations are suitable for initial capacitor selection, but final val- ues should be verified by testing in a prototype or eval- uation circuit. as a general rule, a smaller inductor ripple current results in less output ripple voltage. the output capaci- tor must be also checked against load-transient response requirements. the allowable deviation of the output voltage during fast load transients also deter- mines the output capacitance, its esr, and its equiva- lent series inductance (esl). the output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. the response time (t response ) depends on the closed- loop bandwidth of the converter (see the compensation section). the resistive drop across the output capaci- tors esr, the drop across the capacitors esl ( v esl ), and the capacitor discharge causes a voltage droop during the load step. use a combination of low-esr tantalum/aluminum elec- trolytic or polymer and ceramic capacitors for better transient load and voltage ripple performance. non- leaded capacitors and capacitors in parallel help reduce the esl. keep the maximum output voltage deviation below the tolerable limits of the load. use the following equations to calculate the required esr, esl, and capacitance value during a load step: where i step is the load step, t step is the rise time of the load step, t response is the response time of the con- troller, and f o is the closed-loop crossover frequency. compensation each channel of the MAX15023 provides an internal transconductance amplifier with its inverting input and its output available to the user for external frequency compensation. the flexibility of external compensation for each converter offers wide selection of output filter- ing components, especially the output capacitor. for cost-sensitive applications, use low-esr aluminum electrolytic capacitors; for component-size sensitive applications, use low-esr tantalum, polymer, or ceram- ic capacitors at the output. the high switching frequen- cy of the MAX15023 allows use of ceramic capacitors at the output. choose the small-signal components for the error amplifier to achieve the desired closed-loop bandwidth and phase margin. to choose the appropriate compensation network type, the power-supply poles and zeros, the zero crossover frequency, and the type of the output capacitor must be determined. in a buck converter, the lc filter in the output stage introduces a pair of complex poles at the following fre- quency: the output capacitor and its esr also introduce a zero at: the loop-gain crossover frequency (f o , where the loop gain equals 1 (0db)) should be set below 1/10 the switching frequency: choosing a lower crossover frequency might also help in reducing the effects of noise pickup into the feed- back loop, such as jittery duty cycle. in order to maintain a stable system, two stability crite- ria must be met: 1) the phase shift at the crossover frequency f o , must be less than 180. in other words, the phase margin of the loop must be greater than zero. 2) the gain at the frequency where the phase shift is -180 (gain margin) must be less than 1. f f o sw 10 f esr c zo out = 1 2 f lc po out out = 1 2 esr v i c it v esl vt i t f esr step out step response q esl step step response o = = = ? 1 3 ? v i esr v i cf i vv v vf l esr l q l out sw l in out out in sw = = = ? 8 ()
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller 20 ______________________________________________________________________________________ it is recommended to have a phase margin around +50 to +60 to maintain a robust loop stability and well-behaved transient response. if an electrolytic or large-esr tantalum output capacitor is used, the capacitor esr zero f zo typically occurs between the lc poles and the crossover frequency f o (f po < f zo < f o ). in this case, use a type ii (pi or pro- portional-integral) compensation network. if a ceramic or low-esr tantalum output capacitor is used, the capacitor esr zero typically occurs above the desired crossover frequency f o , that is f po < f o < f zo . in this situation, choose a type iii (pid or propor- tional-integral-derivative) compensation network. type ii compensation network (see figure 4) if f zo is lower than f o and close to f po , the phase lead of the capacitor esr zero almost cancels the phase loss of one of the complex poles of the lc filter around the crossover frequency. therefore, a type ii compen- sation network with a midband zero and a high-fre- quency pole can be used to stabilize the loop. in figure 4, r f and c f introduce a midband zero (f z1 ). r f and c cf in the type ii compensation network also provide a high-frequency pole (f p1 ), which mitigates the effects of the output high-frequency ripple. to calculate the component values for type ii compen- sation network in figure 4, follow the instruction below: 1) calculate the gain of the modulator (gain mod ) composed of the regulators pulse-width modulator, lc filter, feedback divider, and associated circuitry at crossover frequency: where v in is the regulators input voltage, v osc is the amplitude of the ramp in the pulse-width modulator, v fb is the fb_ input voltage set-point (0.6v typically, see electrical characteristics table), and v out is the desired output voltage. the gain of the error amplifier (gain ea ) in midband fre- quencies is: where g m is the transconductance of the error amplifier. the total loop gain as the product of the modulator gain and the error amplifier gain at f o should equal 1. so: therefore: solving for r f : 2) set a midband zero (f z1 ) at 0.75 x f po (to cancel one of the lc poles): solving for c f : 3) place a high-frequency pole at f p1 = 0.5 x f sw (to attenuate the ripple at the switching frequency, f sw ) and calculate c cf using the following equation: c rf c cf fsw f = ? 1 1 c rf f fpo = 1 2075 . f rc f z ff po 1 1 2 075 = = . r vflv v v g esr f osc o out out fb in m = () 2 v v esr fl v v gr in osc o out fb out mf = () 2 1 gain gain mod ea = 1 gain g r ea m f = gain v v esr fl v v mod in osc o out fb out = () 2 v ref r 1 v out r 2 g m r f comp c f c cf figure 4. type ii compensation network
MAX15023 type iii compensation network (see figure 5) if the output capacitor used is a low-esr tantalum or ceramic type, the esr-induced zero frequency is usual- ly above the targeted zero crossover frequency (f o ). in this case, type iii compensation is recommended. type iii compensation provides three poles and two zeros at the following frequencies: two midband zeros (f z1 and f z2 ) cancel the pair of complex poles introduced by the lc filter: f p1 = 0 f p1 introduces a pole at zero frequency (integrator) for nulling dc output voltage errors: depending on the location of the esr zero (f zo ), f p2 can be used to cancel it, or to provide additional atten- uation of the high-frequency output ripple: f p3 attenuates the high-frequency output ripple. the locations of the zeros and poles should be such that the phase margin peaks around f o . ensure that r f >>2/g m (1/g m (min) = 1/600s = 1.67k ) and the parallel resistance of r 1 , r 2 , and r i is greater than 1/g m . otherwise, a 180 phase shift is introduced to the response and will make it unstable. the following procedure is recommended: 1) with r f 10k , place the first zero (f z1 ) at 0.5 x f po : so: 2) the gain of the modulator (gain mod )composed of the regulators pulse-width modulator, lc filter, feedback divider, and associated circuitry at crossover frequency is: the gain of the error amplifier (gain ea ) in midband fre- quencies is: the total loop gain as the product of the modulator gain and the error amplifier gain at f o should be equal to 1. so: therefore: solving for c i : 3) if f po < f o < f zo < f sw /2, the second pole (f p2 ) should be used to cancel f zo . this way, the bode plot of the loop gain plot does not flatten out soon after the 0db crossover, and maintains its -20db/decade slope up to 1/2 the switching frequen- cy. this is likely to occur if the output capacitor is a low-esr tantalum or polymer. then set: f p2 = f zo if a ceramic capacitor is used, then the capacitor esr zero, f zo , is likely to be located even above 1/2 the switching frequency, that is, f po < f o < f sw /2 < f zo . in this case, the frequency of the second pole (f p2 ) should be placed high enough in order not to significantly erode the phase margin at the crossover frequency. for example, it can be set at 5 x f o , so that its contribution to phase loss at the crossover frequency, f o , is only about 11: f p2 = 5 x f o once f p2 is known, calculate r i : r fc i pi = 1 2 2 c vflc vr i osc o out out in f = () 2 v v fc l fcr in osc o out out oif = 1 2 21 2 () gain gain mod ea = 1 gain f c r ea o i f = 2 gain v v fl c mod in osc o out out = 1 2 2 () c rf f fpo = 1 205 . f rc f z ff po 1 1 2 05 = = . f r cc cc p f fcf fcf 3 1 2 = + f rc p ii 2 1 2 = f rc f crr z ff z ii 1 2 1 1 2 1 2 = = + () wide 4.5v to 28v input, dual-output synchronous buck controller ______________________________________________________________________________________ 21
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller 22 ______________________________________________________________________________________ 4) place the second zero (f z2 ) at 0.2 x f o or at f po , whichever is lower and calculate r 1 using the fol- lowing equation: 5) place the third pole (f p3 ) at half the switching fre- quency and calculate c cf : 6) calculate r 2 as: mosfet selection the MAX15023s step-down controller drives two exter- nal logic-level n-channel mosfets as the circuit switch elements. the key selection parameters to choose these mosfets include: ? on-resistance (r ds(on) ) ? maximum drain-to-source voltage (v ds(max) ) ? minimum threshold voltage (v th(min) ) ? total gate charge (qg) ? reverse transfer capacitance (c rss ) ? power dissipation all four n-channel mosfets must be a logic-level type with guaranteed on-resistance specifications at v gs = 4.5v. for maximum efficiency, choose a high-side mosfet (nh_) that has conduction losses equal to the switching losses at the typical input voltage. ensure that the conduction losses at minimum input voltage do not exceed mosfet package thermal limits, or violate the overall thermal budget. also, ensure that the con- duction losses plus switching losses at the maximum input voltage do not exceed package ratings or violate the overall thermal budget. ensure that the MAX15023 dl_ gate drivers can drive a low-side mosfet (nl_). in particular, check that the dv/dt caused by nh_ turn- ing on does not pull up the nl_ gate through nl_s drain-to-gate capacitance. this is the most frequent cause of cross-conduction problems. gate-charge losses are dissipated by the driver and do not heat the mosfet. therefore, if the drive current is taken from the internal ldo regulator, the power dissi- pation due to drive losses must be checked. all mosfets must be selected so that their total gate charge is low enough; therefore, v cc can power all four drivers without overheating the ic: where q g_total is the sum of the gate charges of all four mosfets. power dissipation devices maximum power dissipation depends on the thermal resistance from the die to the ambient environ- ment and the ambient temperature. the thermal resis- tance depends on the device package, pcb copper area, other thermal mass, and airflow. the power dissipated into the package (p t ) depends on the supply configuration (see the typical application circuits ). it can be calculated using the following equation: p t = v in x i in for the circuits of figures 7 and 8: p t = v cc x (i in + i vcc ) where v in and v cc are the voltages at the respective pins, i in is the current at the input of the internal ldo (i in is practically zero for the circuits of figures 7 and 8), i vcc is the current consumed by the internal core and drivers when the internal regulator is unused for 5v supply operation (in = v cc ). see the corresponding typical operating characteristics for the typical curves of i in and i vcc current consumption vs. operating fre- quency at various load capacitance values. pvq f drive in g total sw = _ r v vv r fb out fb 21 = ? c c frc cf f sw f f = () ? 205 1 . r fc r zi i 1 2 1 2 = ? v ref g m r 1 r 2 v out r i comp c i c cf r f c f figure 5. type iii compensation network
MAX15023 to estimate the temperature rise of the die, use the fol- lowing equation: t j = t a + (p t x ja ) where ja is the junction-to-ambient thermal resistance of the package, p t is power dissipated in the device, and t a is the ambient temperature. the ja is 36c/w for the 24-pin tqfn package on multilayer boards, with the conditions specified by the respective jedec stan- dards (jesd51-5, jesd51-7). if actual operating condi- tions significantly deviate from those described in the jedec standards, then an accurate estimation of the junction temperature requires a direct measurement of the case temperature (t c ). then, the junction tempera- ture can be calculated using the following equation: t j = t c + (p t x jc ) use 3c/w as jc thermal resistance for the 24-pin tqfn package. the case-to-ambient thermal resis- tance ( ca ) is dependent on how well the heat is trans- ferred from the pcb to the ambient. therefore, solder the exposed pad of the tqfn package to a large cop- per area to spread heat through the board surface, minimizing the case-to-ambient thermal resistance. use large copper areas to keep the pcb temperature low. boost flying-capacitor selection the MAX15023 uses a bootstrap circuit to generate the necessary gate-to-source voltage to turn on the high- side mosfet. the selected n-channel high-side mos- fet determines the appropriate boost capacitance values (c bst_ in typical application circuits ) according to the following equation: where qg is the total gate charge of the high-side mosfet and v bst_ is the voltage variation allowed on the high-side mosfet driver after turn-on. choose v bst_ such that the available gate drive voltage is not significantly degraded (e.g., v bst_ = 100mv to 300mv) when determining c bst_ . the boost flying- capacitor should be a low-esr ceramic capacitor. a minimum value of 100nf is recommended. applications information pcb layout guidelines make the controller ground connections as follows: cre- ate a small analog ground plane near the ic or use a dedicated internal plane. connect this plane to sgnd and use this plane for the ground connection for the in bypass capacitor, compensation components, feed- back dividers, rt resistor, and lim_ resistors. if possible, place all power components on the top side of the board, and run the power stage currents (espe- cially the one having large high-frequency components) using traces or copper fills on the top side only, without adding vias. on the top side, lay out a large pgnd copper area for the output of channels 1 and 2, and connect the bottom terminals of the high-frequency input capacitors, output capacitors, and the source terminals of the low-side mosfets to that area. then, make a star connection of the sgnd plane to the top copper pgnd area with few vias in the vicinity of the source terminal sensing. do not connect pgnd and sgnd anywhere else. refer to the MAX15023 evaluation kit data sheet for guidance. keep the power traces and load connections short, especially at the ground terminals. this practice is essential for high efficiency and jitter-free operation. use thick copper pcbs (2oz vs. 1oz) to enhance efficiency. place the controller ic adjacent to the synchronous rec- tifier mosfets (nl_) and keep the connections for lx_, pgnd_, dh_, and dl_ short and wide. use multiple small vias to route these signals from the top to the bot- tom side. the gate current traces must be short and wide, measuring 50 mils to 100 mils wide if the low-side mosfet is 1in from the controller ic. connect each pgnd trace from the ic close to the source terminal of the respective low-side mosfet. route high-speed switching nodes (bst_, lx_, dh_, and dl_) away from the sensitive analog areas (rt, comp_, lim_, and fb_). group all sgnd-referred and feedback components close to the ic. keep the fb_ and compensation network nets as small as possible to prevent noise pickup. c qg v bst bst _ _ = wide 4.5v to 28v input, dual-output synchronous buck controller ______________________________________________________________________________________ 23
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller 24 ______________________________________________________________________________________ typical application circuits 3300pf 390pf 33pf MAX15023 q3 fds8880 q2 fds8880 q5 fds6982as-q2 q4 fds6982as-q1 q1 fds8880 2 en1 8 bst1 9 dh1 15 pgood2 19 rt 18 comp2 16 v cc 11 bst2 10 dh2 17 fb2 7 lx1 12 lx2 5 dl1 6 pgnd1 14 dl2 13 pgnd2 24 comp1 23 lim1 21 in 1 fb1 1 f 16.2k 47k 200k 30.1k 20k 2200pf 1.5 r t 33k 10 f 25v 2200pf 3300pf 22pf c bst1 0.22 f c bst2 0.22 f 4.7 f 10 f 25v 20 sgnd 22 lim2 12.1k 12.1k en1 v out1 v out2 v cc pgood2 v cc v in v in 9v to 16v 3 en2 4 pgood1 47k 200k 22.1k 10k 45.3k 1.62k en2 dl1 pgood1 v out1 v cc 0.8 h 3.3 h v in 22 f 6.3v 1500 f 2.5v 22 f 6.3v 22 f 6.3v 22 f 6.3v 10 f 25v 1.5 v out2 figure 6. application diagram (operation from a single-supply rail, v in = 9v to 16v)
MAX15023 typical application circuits (continued) MAX15023 22 dh1 lim2 9 bst2 sgnd 11 20 dh2 in 10 21 lx2 rt 12 19 bst1 lim1 8 23 lx1 comp1 7 24 514 dl1 dl2 415 pgood1 pgood2 613 pgnd1 pgnd2 316 v cc en2 217 fb2 en1 118 comp2 v in 4.5v to 5.5v pgood2 v out2 l2 v in fb1 c8 r6 c6 q1 q2 c2 c in2 c3 c5 c5 r2 r4 r pu1 r8 r7 r1 r10 r9 r t r5 en1 pgood1 v out1 l1 en2 c in1 c bst1 c bst2 c out1 c4 r3 r pu2 q3 v in q4 c out2 figure 7. application diagram (operation with v in = v cc = 5v 10%) wide 4.5v to 28v input, dual-output synchronous buck controller ______________________________________________________________________________________ 25
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller 26 ______________________________________________________________________________________ typical application circuits (continued) MAX15023 22 dh1 lim2 9 bst2 sgnd 11 20 dh2 in 10 21 lx2 rt 12 19 bst1 lim1 8 23 lx1 comp1 7 24 514 dl1 dl2 415 pgood1 pgood2 613 pgnd1 pgnd2 316 v cc en2 217 fb2 en1 118 comp2 v aux 4.5v to 5.5v pgood2 v out2 l2 v in 3.3v fb1 c8 r6 c6 q1 q2 c2 c in2 c3 c5 c5 r2 r4 r pu1 r8 v in 3.3v r7 r1 r10 r9 r t r5 en1 pgood1 v out1 l1 en2 c in1 c bst1 c bst2 c out1 c4 r3 r pu2 q3 q4 c out2 figure 8. application diagram (operation with auxiliary 5v supply and 3.3v bus)
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller ______________________________________________________________________________________ 27 package information for the latest package outline information, go to www.maxim-ic.com/packages . chip information process: bicmos package type package code document no. 24 tqfn-ep t2444-4 21-0139
MAX15023 wide 4.5v to 28v input, dual-output synchronous buck controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 7/08 initial release 1 2/09 updated electrical characteristics , current-limit circuit (lim_) , and setting the enable input (en_) sections . 4, 15, 16

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